The present invention relates to a semiconductor memory device, more specifically to a semiconductor memory device and a method for fabricating the same which can fabricate a DRAM (Dynamic Random Access Memory) of high integration and high efficiency at low costs.
A DRAM is a semiconductor device which may comprise one transistor and one capacitor, and its structures and methods for fabricating the structures have been conventionally studied for fabricating semiconductor devices of high density, high integration and high efficiency.
To achieve higher integration of a DRAM, it is effective to make the capacitor area smaller. The capacitance reduction accompanies soft error resistance degradation. This is a disadvantage. Lower electric power consumption of the device as well as higher integration has achieved, but the electric power consumption reduction makes the junction capacitance of the device more influential, which is a barrier to higher speed operation of the device.
As effective means to solve these disadvantages, a method for fabricating a DRAM using an SOI (Semiconductor On Insulator) substrate in place of the conventional silicon substrate has been proposed.
By applying the SOI structure to a DRAM, perfect isolation between devices can be made possible, and the soft error immunity and latch-up resistance can be much improved. The junction area can be reduced, and high speed operation at low electric power consumption can be made possible. Furthermore, the soft error immunity can be thus improved, which allows a smaller capacitance. The capacitor forming process can be accordingly simplified.
Also proposed has been the so-called bonded SOI technique in which another substrate is adhered to a surface of a silicon substrate with an insulating portion formed on, which is on the side of the insulating portion, and the silicon substrate is polished to form a semiconductor layer on the insulating portion. A DRAM using this bonded SOI technique is disclosed in Japanese Patent Laid-Open Publication No. Tokkaihei 04-225276/1992 and Japanese Patent Laid-Open Publication No. Tokkaihei 06104410/1994.
The DRAM using the above-described conventional SOI structure can simplify the capacitor forming process to thereby decrease costs, but cost increase due to the use of the SOI structure exceeds the cost decrease, sometimes with the result of higher fabrication costs.
In devices using the above-described conventional SOI structure, the devices are fabricated after the SOI substrate is formed. The substrate is subjected to all heat treatments for forming the devices. Because SOI substrates are usually more susceptible of heat treatments than the usual substrates, the wafers are easily deformed, and crystal defects are easily introduced. As a result, the fabrication yields are often low.
In the DRAM using the above-described SOI structure, for the purpose of reducing this disadvantage as much as possible, a material having a thermal diffusion coefficient equal to that of the SOI layer supported on the support substrate, e.g., a semiconductor substrate of the same single crystal as the SOI layer, must be used. This often adds to fabrication costs of the DRAM.
In the bonded SOI, devices are formed on the SOI layer which is adhered thereto the substrate and polished. Accordingly it is necessary to finish the polished surface in a speculum of high precision. The polishing step often adds to fabrication costs.
To form the usual SOI substrate, the polishing step of planarizing a surface of a semiconductor substrate before the substrate is adhered to, and the polishing step of polishing the adhered semiconductor substrate to a thin film to form the SOI layer are necessary. This often adds to fabrication costs.
The use of the SOI structure makes it difficult to apply back bias to the channel regions of transistors, and the source-drain voltage resistance is often degraded due to charges accumulated in the back gates.
To prevent erroneous operation of memories, it is effective to cover the bit lines with shield electrodes. In the conventional DRAM structure, however, a number of lines and capacitors are formed on the bit line, which makes it difficult to cover the bit lines with the shield electrodes.
The above-described disadvantages make it difficult to form memories of high soft error immunity and reliability, which makes it accordingly difficult to reduce the capacitance to thereby simplify the fabrication process.
An object of the present invention is to provide a semiconductor memory device structure which permits a semiconductor memory device including the SOI structure to be fabricated at low costs without fabrication yield decrease, and a method for fabricating the same.